Validation and Verification System Engineer (FPGA) (Closed)

Responsibilities

• Reviewing verification plan/matrix.
• Reviewing verification environment and implementing updates
• Developing test cases
• Debugging failing cases
• Completing 100% functional and code coverage
• Participating in peer and developmental reviews
• Supporting gate-level simulation

Mandatory Skills

• Design requires the following skill set:
  • Experience with complex and large-scale FPGA development
  • Experience with the latest industry FPGA development tools, design flow and verification methodology, such as UVM and OVM
  • Working knowledge with implementing FPGA designs using industry standard FPGA development languages, such as Verilog and System Verilog
  • Extensive knowledge of best industry practices in electronics and FPGA development, implementation, testing, and verification
  • Knowledge in the implementation of electronics (digital and analog)
  • Excellent oral/written communication and presentation skills
  • Ability to work effectively in a team
• Verification requires the following skill set:
  • Experience with complex and large-scale FPGA development.
  • Experience with the latest industry FPGA verification methodologies utilizing UVM and SystemVerilog performed on Mentor Questa sim environment.
  • Experience in all aspects of design verification:
    • Verification planning (Verification plan & Verification matrix)           
    • Verification testbench development (block-level & system-level)
    • Test case writing
    • Coverage closure (Functional & code-coverage)
      • Tools:
        • Simulation (Mentor Questa)
        • Continuous integration (Bamboo)
        • Configuration management (git)
        • Bug-tracking (JIRA)
        • Formal verification (0-in)
        • Excellent oral/written communication and presentation skills
        • Ability to work effectively in a team

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